1. Field of the Invention
The present invention relates to a memory access control circuit in a computer system, and more specifically to a memory access control circuit for inhibiting a fraudulent access by detecting an access to a region to be protected on a memory.
2. Description of Related Art
In the prior art, development of a computer program needs a considerable amount of time. A computer program developer covers the development expense by selling the program. However, it is possible that a third person prepares a program for reading a program and data on a memory, and copies the program and data stored in the memory by use of that program. However, if this copying can be easily performed, it becomes difficult to cover the development expense. In addition, in an encryption circuit in which an encryption processing routine and data used in an encryption algorithm are stored in a memory, if these information are read from the memory, a plain text before encryption will be stolen.
Under the above mentioned circumstance, a memory access control circuit for inhibiting the fraudulent access to the memory has been proposed (See for example Japanese Patent Application Pre-examination Publication No. JP-A-59-11600, the content of which is incorporated by reference in its entirety into this application). This JP-A-59-11600 claims Convention Priorities based on four U.S. patent applications, which have now issued as U.S. Pat. Nos. 4,521,852, 4,521,853, 4,590,552 and 4,603,381, the content of which is incorporated by reference in its entirety into this application. FIG. 1 is a block diagram of the prior art memory access control circuit disclosed by JP-A-59-11600.
This prior art memory access control circuit includes a CPU (control processing unit) 31, a nonvolatile memory 32, a temporary memory (RAM) 33, an external interface 34, an address bus 35, a data bus 36, program guard bits 37 indicating the protection situation of information stored in the nonvolatile memory 32, an address logic 38 for discriminating the access to nonvolatile memory 32, an external interface inhibit logic 39 for inhibiting the operation of the external interface 34, an operation inhibiting buffer 40 for inhibiting the operation of the nonvolatile memory 32, an operation inhibiting buffer 41 for inhibiting the operation of the temporary memory 33, and an instruction acquisition logic 42 for determining when the instruction acquisition takes place, which are coupled as shown.
With this arrangement, this memory access control circuit inhibits transfer of information from a region to be protected in the nonvolatile memory 32 or the temporary memory 33 to a region not to be protected. Thus, a third person can no longer read out the data to be protected in the nonvolatile memory 32 to the temporary memory 33 by executing a program on the temporary memory 33.
However, since the prior art memory access control circuit inhibits only the transfer of information from one memory to another, it cannot inhibit to temporarily read out from the data to be protected in the memory to a general purpose register such as an accumulator in the CPU, and to perform any arithmetic operation for the read-out data and to output the result of the arithmetic operation into a region not to be protected in the memory. In this case, the original data to be protected can be known by obtaining the result of arithmetic operation.
For example, after the data in the region to be protected is read out to the accumulator and a simple arithmetic operation for adding "0" into the read-out data is executed, if the result of arithmetic operation is read out, the original data to be protected can be easily known. Alternatively, by investigating the change of the status in a status flag (for example, a carry flag) internally provided in the CPU when an arithmetic operation is executed, the original data to be protected can be indirectly known.